|
Neuromorphic Computing Hardware Design A "natural" candidate for emerging computer architectures is the concept of neuromorphic systems or computational networks constructed from neural networks. Neuromorphic computer architectures are inspired by biology in that their operation is based on our best understanding of the functionality of the mammalian brain. While artificial neural networks can be constructed from conventional electronic devices such as transistors, emerging nanoscale devices (e.g. memristors) exhibit properties particularly well suited for building high density, power-efficient neuromorphic systems. As part of our research, we are exploring how memristive devices can be exploited as synaptic elements in complex neural networks. This approach of "memristors as synapses" has been applied to several neuromorphic architectures, including brain-state-in-a-box (BSB) and popular Hopfield networks. Furthermore, in contrast to most silicon based reconfigurable devices, neuromorphic systems learn or are trained in much the same way as animals must learn. To this end, we are also engaged in the exploration of training methods for the memristor-based neuromorphic systems we design. We are exploring different emerging devices for low-power, efficient neuromorphic implementation. I focus on developing robust and useful models for these devices including biomolecular memristor and memcapacitor, Insulator-metal transition devices, transition metal oxide devices and 2-D Graphene resonant tunneling diode |
I am currently collaborating with Dr. Nicole McFarlane(Link)on modeling and SPICE implementation of Perimeter gated single photon avalanche diodes to be used in Silicon Photomultiplier(SiPM).
|
I have also worked on modeling emerging devices such as novolatile and volatile memristors. This includes analysis and modeling of Electroforming in Transition Metal Oxide-based non-volatile Memristors(NVM) and explored its impact on crossbar Array Density, developing a SPICE model for Insulator metal transition(IMT) devices to be used as an artificial neuron, modeling and SPICE implementation of soft-matter biomolecular memristors and memcapacitors. I am currently developing a SPICE model for 2D Graphene resonant tunneling diode (RTD) device in collaboration with Dr. Gong Gu(Link) to design a compact neuromorphic system combining NVM(synapse) and IMT+RTD(neuron) devices. More on modeling for neuromorphic systems can be found in the section above (Neuromorphic Computing` |
|
Worked on Designing a low power Potentiostat for an implantable blood glucose sensor using EDA tools in 180 nm Process. Optimized a transconductance enhanced body driven operational amplifier for low power consumption and high linearity against glucose concentration. on designing a fully integrated system for apnea detection in neonatal infants. It included a prototype device with the pyroelectric sensor and wireless telemetry in 0.5 um CMOS process. Designed separate blocks like Operational transconductance Amplifier (OTA), hysteresis comparator, Time to Voltage Converter (TVC), counter and detection scheme to meet system requirements.Developed a wireless transmission and reception scheme for continuous health monitoring using CC2530 AIR module from Anaren with MSP 430 Launchpad using MSP 430G2553 microcontroller from Texas Instruments. Other Circuit design works include RF Injection-Locked Frequency Divider Based on Relaxation Oscillator, Automatic Placement and Routing of successive approximation register(SAR) Analog-Digital Converter(ADC) with capacitor bank placement using common centroid algorithm, common centroid alrogithm , development of a Pole Swap Compensation Technique to aid High Temperature Linear Voltage Regulator Design, low power Reconfigurable Pipeline ADC for Biomedical applications, Terahertz Frequency Generation in 90nm Process Using Linear Superposition etc. |
|
The term "Chaos" is used in Mathematics to refer to behavior of some dynamical systems capable of generating aperiodic patterns. Chaotic system is highly sensitive to initial condition. In the long run, a small change in initial value of a chaotic system results in a completely differnt behavior. Interestingly chaotic system can be used to implement reconfigurable computing unit. Logic gates are building blocks of a digital computing system. We can find all logic functions from a single chaotic hardware configured differently. The most interesting part of this reconfigurability is that similar logic operations can be configured differently too where each one exhibits completely different physical characteristics such as power consumption, delay etc. This properties of chaotic system can be leverage to build each computing system in unique ways exhibiting unique power, timing characteristics. Power, timing characteristics are two major side channels that are widely reported to be used in reverse engineering a secret code or data. Such reverse engineering tasks are often based on template attack where a computing system is profiled based on its side channel characteristics. Profiling information is used then to reverse engineer another system as each system is similar in terms of their side channel characteristics. Chaos based system can defend such vulnerabilities because each system is unique here and therefore profiling one system cannot be used to reverse engineer another. |
|
Memristive crossbar memory is one of the prominent emerging memory technologies. Memristor, being a nanoelectronic device provides advantages from many perspectives over conventinoal CMOS technology such as high integration, lower power consumption etc. However, one of the major cons of memristive system is the reliability. Due to process variations memristive system lacks reliability. Another common problem that affects the reliability of a memristive crossbar system is the sneak path currents. Sneak path currents cause both read and write disturbances in memristive crossbar memory array. However a selector device with each memory cell suffices the problem with a cost of additional area overhead Sneak path currents in memristive crossbar architecture can be applied interestingly in memory integrity checking applications. As sneak path currents carry information from all memory cells comprising the path, it can be used to generate a signature of the overall memory state. This signature represents the present state of the memory. If the memory state is unchanged, the signature remains the same. However, if the memory state changes, the signature changes significantly which is way to detect any unauthorized modification of the memory. |